
module LinearTable(
  input  wire       clk,
  input  wire       rst_n,
  input  wire [7:0] addr,
  output reg  [9:0] data
);

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	data <= #1 10'b0;
    else
	case(addr[6:0])
        7'h00: data <= #1 {addr[7], 9'b111111111};
        7'h01: data <= #1 {addr[7], 9'b111101001};
        7'h02: data <= #1 {addr[7], 9'b111010100};
        7'h03: data <= #1 {addr[7], 9'b111000000};
        7'h04: data <= #1 {addr[7], 9'b110101101};
        7'h05: data <= #1 {addr[7], 9'b110011011};
        7'h06: data <= #1 {addr[7], 9'b110001010};
        7'h07: data <= #1 {addr[7], 9'b101111001};
        7'h08: data <= #1 {addr[7], 9'b101101001};
        7'h09: data <= #1 {addr[7], 9'b101011010};
        7'h0a: data <= #1 {addr[7], 9'b101001011};
        7'h0b: data <= #1 {addr[7], 9'b100111101};
        7'h0c: data <= #1 {addr[7], 9'b100110000};
        7'h0d: data <= #1 {addr[7], 9'b100100011};
        7'h0e: data <= #1 {addr[7], 9'b100010111};
        7'h0f: data <= #1 {addr[7], 9'b100001011};
        7'h10: data <= #1 {addr[7], 9'b100000000};
        7'h11: data <= #1 {addr[7], 9'b011110101};
        7'h12: data <= #1 {addr[7], 9'b011101010};
        7'h13: data <= #1 {addr[7], 9'b011100000};
        7'h14: data <= #1 {addr[7], 9'b011010111};
        7'h15: data <= #1 {addr[7], 9'b011001110};
        7'h16: data <= #1 {addr[7], 9'b011000101};
        7'h17: data <= #1 {addr[7], 9'b010111101};
        7'h18: data <= #1 {addr[7], 9'b010110101};
        7'h19: data <= #1 {addr[7], 9'b010101101};
        7'h1a: data <= #1 {addr[7], 9'b010100110};
        7'h1b: data <= #1 {addr[7], 9'b010011111};
        7'h1c: data <= #1 {addr[7], 9'b010011000};
        7'h1d: data <= #1 {addr[7], 9'b010010010};
        7'h1e: data <= #1 {addr[7], 9'b010001011};
        7'h1f: data <= #1 {addr[7], 9'b010000110};
        7'h20: data <= #1 {addr[7], 9'b010000000};
        7'h21: data <= #1 {addr[7], 9'b001111010};
        7'h22: data <= #1 {addr[7], 9'b001110101};
        7'h23: data <= #1 {addr[7], 9'b001110000};
        7'h24: data <= #1 {addr[7], 9'b001101011};
        7'h25: data <= #1 {addr[7], 9'b001100111};
        7'h26: data <= #1 {addr[7], 9'b001100011};
        7'h27: data <= #1 {addr[7], 9'b001011110};
        7'h28: data <= #1 {addr[7], 9'b001011010};
        7'h29: data <= #1 {addr[7], 9'b001010111};
        7'h2a: data <= #1 {addr[7], 9'b001010011};
        7'h2b: data <= #1 {addr[7], 9'b001001111};
        7'h2c: data <= #1 {addr[7], 9'b001001100};
        7'h2d: data <= #1 {addr[7], 9'b001001001};
        7'h2e: data <= #1 {addr[7], 9'b001000110};
        7'h2f: data <= #1 {addr[7], 9'b001000011};
        7'h30: data <= #1 {addr[7], 9'b001000000};
        7'h31: data <= #1 {addr[7], 9'b000111101};
        7'h32: data <= #1 {addr[7], 9'b000111011};
        7'h33: data <= #1 {addr[7], 9'b000111000};
        7'h34: data <= #1 {addr[7], 9'b000110110};
        7'h35: data <= #1 {addr[7], 9'b000110011};
        7'h36: data <= #1 {addr[7], 9'b000110001};
        7'h37: data <= #1 {addr[7], 9'b000101111};
        7'h38: data <= #1 {addr[7], 9'b000101101};
        7'h39: data <= #1 {addr[7], 9'b000101011};
        7'h3a: data <= #1 {addr[7], 9'b000101001};
        7'h3b: data <= #1 {addr[7], 9'b000101000};
        7'h3c: data <= #1 {addr[7], 9'b000100110};
        7'h3d: data <= #1 {addr[7], 9'b000100100};
        7'h3e: data <= #1 {addr[7], 9'b000100011};
        7'h3f: data <= #1 {addr[7], 9'b000100001};
        7'h40: data <= #1 {addr[7], 9'b000100000};
        7'h41: data <= #1 {addr[7], 9'b000011110};
        7'h42: data <= #1 {addr[7], 9'b000011101};
        7'h43: data <= #1 {addr[7], 9'b000011100};
        7'h44: data <= #1 {addr[7], 9'b000011011};
        7'h45: data <= #1 {addr[7], 9'b000011001};
        7'h46: data <= #1 {addr[7], 9'b000011000};
        7'h47: data <= #1 {addr[7], 9'b000010111};
        7'h48: data <= #1 {addr[7], 9'b000010110};
        7'h49: data <= #1 {addr[7], 9'b000010101};
        7'h4a: data <= #1 {addr[7], 9'b000010100};
        7'h4b: data <= #1 {addr[7], 9'b000010100};
        7'h4c: data <= #1 {addr[7], 9'b000010011};
        7'h4d: data <= #1 {addr[7], 9'b000010010};
        7'h4e: data <= #1 {addr[7], 9'b000010001};
        7'h4f: data <= #1 {addr[7], 9'b000010000};
        7'h50: data <= #1 {addr[7], 9'b000010000};
        7'h51: data <= #1 {addr[7], 9'b000001111};
        7'h52: data <= #1 {addr[7], 9'b000001110};
        7'h53: data <= #1 {addr[7], 9'b000001110};
        7'h54: data <= #1 {addr[7], 9'b000001101};
        7'h55: data <= #1 {addr[7], 9'b000001101};
        7'h56: data <= #1 {addr[7], 9'b000001100};
        7'h57: data <= #1 {addr[7], 9'b000001011};
        7'h58: data <= #1 {addr[7], 9'b000001011};
        7'h59: data <= #1 {addr[7], 9'b000001010};
        7'h5a: data <= #1 {addr[7], 9'b000001010};
        7'h5b: data <= #1 {addr[7], 9'b000001010};
        7'h5c: data <= #1 {addr[7], 9'b000001001};
        7'h5d: data <= #1 {addr[7], 9'b000001001};
        7'h5e: data <= #1 {addr[7], 9'b000001000};
        7'h5f: data <= #1 {addr[7], 9'b000001000};
        7'h60: data <= #1 {addr[7], 9'b000001000};
        7'h61: data <= #1 {addr[7], 9'b000000111};
        7'h62: data <= #1 {addr[7], 9'b000000111};
        7'h63: data <= #1 {addr[7], 9'b000000111};
        7'h64: data <= #1 {addr[7], 9'b000000110};
        7'h65: data <= #1 {addr[7], 9'b000000110};
        7'h66: data <= #1 {addr[7], 9'b000000110};
        7'h67: data <= #1 {addr[7], 9'b000000101};
        7'h68: data <= #1 {addr[7], 9'b000000101};
        7'h69: data <= #1 {addr[7], 9'b000000101};
        7'h6a: data <= #1 {addr[7], 9'b000000101};
        7'h6b: data <= #1 {addr[7], 9'b000000101};
        7'h6c: data <= #1 {addr[7], 9'b000000100};
        7'h6d: data <= #1 {addr[7], 9'b000000100};
        7'h6e: data <= #1 {addr[7], 9'b000000100};
        7'h6f: data <= #1 {addr[7], 9'b000000100};
        7'h70: data <= #1 {addr[7], 9'b000000100};
        7'h71: data <= #1 {addr[7], 9'b000000011};
        7'h72: data <= #1 {addr[7], 9'b000000011};
        7'h73: data <= #1 {addr[7], 9'b000000011};
        7'h74: data <= #1 {addr[7], 9'b000000011};
        7'h75: data <= #1 {addr[7], 9'b000000011};
        7'h76: data <= #1 {addr[7], 9'b000000011};
        7'h77: data <= #1 {addr[7], 9'b000000011};
        7'h78: data <= #1 {addr[7], 9'b000000010};
        7'h79: data <= #1 {addr[7], 9'b000000010};
        7'h7a: data <= #1 {addr[7], 9'b000000010};
        7'h7b: data <= #1 {addr[7], 9'b000000010};
        7'h7c: data <= #1 {addr[7], 9'b000000010};
        7'h7d: data <= #1 {addr[7], 9'b000000010};
        7'h7e: data <= #1 {addr[7], 9'b000000010};
        7'h7f: data <= #1 {addr[7], 9'b000000000};
	endcase
end

endmodule

